![]() G06F12/02- Addressing or allocation Relocation.G06F12/00- Accessing, addressing or allocating within memory systems or architectures.dynamic instruction scheduling, out of order instruction execution of compound instructions dynamic instruction scheduling, out of order instruction execution G06F9/38- Concurrent instruction execution, e.g.G06F9/30181- Instruction operation extension or modification.G06F9/30- Arrangements for executing machine instructions, e.g.using an internal store of processing equipment to receive or retain programs control units using stored programs, i.e. G06F9/06- Arrangements for program control, e.g.G06F9/00- Arrangements for program control, e.g.G06- COMPUTING CALCULATING OR COUNTING.239000003795 chemical substances by application Substances 0.000 description 1.238000004519 manufacturing process Methods 0.000 description 2.230000000875 corresponding Effects 0.000 claims description 7.238000000034 method Methods 0.000 title abstract description 7.230000004927 fusion Effects 0.000 title claims abstract description 19.Priority to JP2014241108A priority patent/JP5902285B2/en Priority to US15/143,518 priority patent/US20160378487A1/en Priority to US15/143,520 priority patent/US10649783B2/en Priority to US15/143,522 priority patent/US20160246600A1/en Publication of US9690591B2 publication Critical patent/US9690591B2/en Application granted granted Critical Status Active legal-status Critical Current Adjusted expiration legal-status Critical Links Assignors: RAGHUVANSHI, PANKAJ, GABOR, RON, OUZIEL, IDO, RAPPOPORT, LIHU, VALENTINE, ROBERT Publication of US20100115248A1 publication Critical patent/US20100115248A1/en First worldwide family litigation filed litigation Critical (A1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.) Filing date Publication date Family has litigation Application filed by Intel Corp filed Critical Intel Corp Priority to US12/290,395 priority Critical patent/US9690591B2/en Priority to JP2011534680A priority patent/JP2012507794A/en Priority to PCT/US2009/062219 priority patent/WO2010056511A2/en Priority to KR1020117007623A priority patent/KR101258762B1/en Priority to BRPI0920782A priority patent/BRPI0920782B1/en Priority to TW098136712A priority patent/TWI455023B/en Priority to CN201410054184.XA priority patent/CN103870243B/en Priority to DE102009051388A priority patent/DE102009051388A1/en Priority to CN200910253081.5A priority patent/CN101901128B/en Priority to BRPI0904287-3A priority patent/BRPI0904287A2/en Assigned to INTEL CORPORATION reassignment INTEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Original Assignee Intel Corp Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.) ( en Inventor Ido Ouziel Lihu Rappoport Robert Valentine Ron Gabor Pankaj Raghuvanshi Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.) Granted Application number US12/290,395 Other versions US9690591B2 Google Patents Technique for promoting efficient instruction fusionĭownload PDF Info Publication number US20100115248A1 US20100115248A1 US12/290,395 US29039508A US2010115248A1 US 20100115248 A1 US20100115248 A1 US 20100115248A1 US 29039508 A US29039508 A US 29039508A US 2010115248 A1 US2010115248 A1 US 2010115248A1 Authority US United States Prior art keywords instruction fusible stored instructions cache Prior art date Legal status (The legal status is an assumption and is not a legal conclusion. Google Patents US20100115248A1 - Technique for promoting efficient instruction fusion US20100115248A1 - Technique for promoting efficient instruction fusion
0 Comments
Leave a Reply. |